{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:49:41Z","timestamp":1729615781214,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2003.1206205","type":"proceedings-article","created":{"date-parts":[[2003,11,20]],"date-time":"2003-11-20T20:19:26Z","timestamp":1069359566000},"page":"V-121-V-124","source":"Crossref","is-referenced-by-count":0,"title":["A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder"],"prefix":"10.1109","volume":"5","author":[{"family":"Hwang-Cherng Chow","sequence":"first","affiliation":[]},{"family":"I-Chyn Wey","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"crossref","first-page":"457","DOI":"10.1109\/ISCAS.2002.1009876","article-title":"A 3.3V 1GHz high speed pipelined Booth multiplier","volume":"1","author":"chow","year":"2002","journal-title":"Proc IEEE International Symp on Circuits and Systems"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"692","DOI":"10.1109\/12.863039","article-title":"High-Speed Booth Encoded Parallel Multiplier Design","volume":"49","author":"yeh","year":"2000","journal-title":"IEEE Trans on Computers"},{"key":"ref10","first-page":"80","article-title":"A 1.25 GHz 32-bit Tree-Structured Carry Lookahead Adder","volume":"4","author":"wang","year":"2001","journal-title":"Proc IEEE International Symp on Circuits and Systems"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/4.839918"},{"key":"ref11","first-page":"84","article-title":"A 2.8ns 30uw\/MHz Area-Efficient 32-B Manchester Carry-Bypass Adder","volume":"4","author":"eriksson","year":"2001","journal-title":"Proc IEEE International Symp on Circuits and Systems"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"498","DOI":"10.1109\/5.371964","article-title":"Minimizing Power Consumption in Digital CMOS Circuits","volume":"83","author":"chandrakasan","year":"1995","journal-title":"Proc IEEE"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/4.551912"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/4.18596"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"214","DOI":"10.1145\/263272.263337","article-title":"Minimizing energy dissipation in high-speed multipliers","author":"fried","year":"1997","journal-title":"Proceedings of 1997 International Symposium on Low Power Electronics and Design LPE"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/82.823541"},{"key":"ref1","first-page":"240","article-title":"Basic VLSI Design","author":"pucknell","year":"1994"}],"event":{"acronym":"ISCAS-03","name":"ISCAS 2003. International Symposium on Circuits and Systems","location":"Bangkok, Thailand"},"container-title":["Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8570\/27139\/01206205.pdf?arnumber=1206205","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,27]],"date-time":"2020-03-27T01:40:04Z","timestamp":1585273204000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1206205\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2003.1206205","relation":{},"subject":[]}}