{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:40:20Z","timestamp":1729662020775,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1464674","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T13:52:28Z","timestamp":1122472348000},"page":"660-663","source":"Crossref","is-referenced-by-count":0,"title":["Non-Interleaving Architecture for Hardware Implementation of Modular Multiplication"],"prefix":"10.1109","author":[{"family":"Qiang Liu","sequence":"first","affiliation":[]},{"family":"Dong Tong","sequence":"additional","affiliation":[]},{"family":"Xu Cheng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","first-page":"379","article-title":"fast montgomery modular multiplication and rsa cryptographic processor architectures","volume":"1","author":"mcivor","year":"2003","journal-title":"Proc 37th Asilomar Conference on Signals Systems and Computers"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1145\/503053.503055"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1205791"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812308"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/12.936241"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/92.820767"},{"journal-title":"The Art of Computer Programming Volume 2 Seminumerical Algorithms","year":"1998","author":"knuth","key":"14"},{"key":"11","article-title":"architectural approaches to hardware implementation of rsa","author":"liu","year":"0","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1993.378085"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/12.277287"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269231"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.2307\/2007970"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1145\/359340.359342"},{"key":"10","first-page":"467","article-title":"a regular parallel rsa processor","volume":"3","author":"liu","year":"2004","journal-title":"Proc IEEE 47th International Midwest Symposium on Circuits and Systems (MWSCAS 2004)"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/370155.370419"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/12.210181"},{"key":"5","doi-asserted-by":"crossref","first-page":"650","DOI":"10.1109\/ISCAS.2001.922321","article-title":"two implementation methods of a 1024 bit rsa cryptoprocesor based on modified montgomery algorithm","volume":"4","author":"kwon","year":"2001","journal-title":"Proc 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001)"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1049\/el:19991230"},{"key":"9","first-page":"33","article-title":"towards an fpga architecture optimized for public-key algorithms","volume":"3844","author":"elbirt","year":"1999","journal-title":"Proc SPIE's Symposium on Voice Video and Data Communications"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1999.762831"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01464674.pdf?arnumber=1464674","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T17:35:24Z","timestamp":1497634524000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1464674\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1464674","relation":{},"subject":[]}}