{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,1]],"date-time":"2025-07-01T10:30:19Z","timestamp":1751365819762},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1464679","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T13:52:28Z","timestamp":1122472348000},"page":"680-683","source":"Crossref","is-referenced-by-count":10,"title":["High-level synthesis under I\/O Timing and Memory constraints"],"prefix":"10.1109","author":[{"given":"P.","family":"Coussy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Corre","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Bomel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Senn","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Martin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Codesimulink","year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379030"},{"journal-title":"Tool for DSP","year":"0","author":"gaut","key":"10"},{"key":"1","article-title":"matlab\/simulink-based high-level synthesis of discrete-time and continuous-time modulators","author":"ruiz-amaya","year":"2004","journal-title":"Proc of DATE"},{"key":"7","article-title":"communication and timing constraints analysis for ip design and integration","author":"coussy","year":"0","journal-title":"In Proc of IFIP WG 10 5 VLSI-SOC Conference 2003"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICPP.1993.181"},{"key":"5","article-title":"multi-dimensional interleaving for timeand-memory design optimization","author":"passos","year":"0","journal-title":"Proc of ICCD 1995"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217514"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/1016720.1016733"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2004.1327043"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01464679.pdf?arnumber=1464679","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T19:19:38Z","timestamp":1489519178000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1464679\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1464679","relation":{},"subject":[]}}