{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,29]],"date-time":"2025-03-29T16:17:19Z","timestamp":1743265039013,"version":"3.28.0"},"reference-count":8,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1464776","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T17:52:28Z","timestamp":1122486748000},"page":"1066-1069","source":"Crossref","is-referenced-by-count":11,"title":["A Novel CMOS Logic Style with Data Independent Power Consumption"],"prefix":"10.1109","author":[{"given":"M.","family":"Aigner","sequence":"first","affiliation":[]},{"given":"S.","family":"Mangard","sequence":"additional","affiliation":[]},{"given":"R.","family":"Menicocci","sequence":"additional","affiliation":[]},{"given":"M.","family":"Olivieri","sequence":"additional","affiliation":[]},{"given":"G.","family":"Scotti","sequence":"additional","affiliation":[]},{"given":"A.","family":"Trifiletti","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"9","article-title":"design principles for tamper- resistant smart card processors","author":"koemmerling 0","year":"1999","journal-title":"USENIX Workshop on Smart Card Technology"},{"key":"2","doi-asserted-by":"crossref","first-page":"388","DOI":"10.1007\/3-540-48405-1_25","article-title":"differential power analysis","volume":"1666","author":"kocher","year":"1999","journal-title":"Lecture Notes in Computer Science"},{"key":"1","first-page":"55","article-title":"information leakage attacks against smart card implementations of cryptographic algorithms and countermeasures - a survey","author":"hess","year":"2000","journal-title":"Eurosmart Security Conference"},{"key":"7","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","author":"tiri","year":"2002","journal-title":"Proceedings of the 28th European Solid-State Circuits Conference ESSCIRC"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004593"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44499-8_19"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44499-8_20"},{"key":"8","doi-asserted-by":"crossref","first-page":"1028","DOI":"10.1109\/TVLSI.2004.827563","article-title":"sequential delay budgeting with interconnect prediction","volume":"12","author":"yeh","year":"2004","journal-title":"IEEE Transactions on very large scale integration Systems"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01464776.pdf?arnumber=1464776","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T16:03:17Z","timestamp":1602691397000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/1464776"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":8,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1464776","relation":{},"subject":[]}}