{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,27]],"date-time":"2025-05-27T15:48:02Z","timestamp":1748360882326,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1465896","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T13:52:28Z","timestamp":1122472348000},"page":"5557-5560","source":"Crossref","is-referenced-by-count":15,"title":["A Background Correction Technique for Timing Errors in Time-Interleaved Analog-to-Digital Converters."],"prefix":"10.1109","author":[{"given":"E.","family":"Iroaga","sequence":"first","affiliation":[]},{"given":"B.","family":"Murmann","sequence":"additional","affiliation":[]},{"given":"L.","family":"Nathawad","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.735530"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.608758"},{"key":"10","first-page":"330","article-title":"a digital technique for reducing clock jitter effects in time-interleaved a\/d converter","volume":"2","author":"jin","year":"1999","journal-title":"IEEE International Symposium on Circuits and Systems"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1980.1051512"},{"article-title":"a high speed parallel pipeline a\/d converter technique in cmos","year":"1994","author":"conroy","key":"7"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.821302"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/82.850419"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/4.735531"},{"key":"9","first-page":"88","author":"burden","year":"1981","journal-title":"Numerical Analysis"},{"article-title":"digital background calibration of time-interleaved analog-to-digital converters","year":"2001","author":"jamal","key":"8"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2004.832755"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.704123"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01465896.pdf?arnumber=1465896","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T19:41:13Z","timestamp":1489520473000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1465896\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1465896","relation":{},"subject":[]}}