{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,3]],"date-time":"2025-12-03T17:28:21Z","timestamp":1764782901086},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1465916","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T13:52:28Z","timestamp":1122472348000},"page":"5637-5640","source":"Crossref","is-referenced-by-count":6,"title":["Design of MOS Current Mode Logic Gates \u2013 Computing the Limits of Voltage Swing and Bias Current"],"prefix":"10.1109","author":[{"given":"G.","family":"Caruso","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"0","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/SOC.2003.1241479"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/81.244904"},{"journal-title":"An Analysis of MOS Current Mode Logic for Low Power and High Performance Digital Logic","year":"0","author":"musicer","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2003.811023"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01465916.pdf?arnumber=1465916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T20:54:51Z","timestamp":1489524891000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1465916\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1465916","relation":{},"subject":[]}}