{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T11:25:33Z","timestamp":1725708333475},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1465920","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T17:52:28Z","timestamp":1122486748000},"page":"5653-5656","source":"Crossref","is-referenced-by-count":2,"title":["FPGA Technology Mapping Optimization by Rewiring Algorithms"],"prefix":"10.1109","author":[{"family":"Wai-Chung Tang","sequence":"first","affiliation":[]},{"family":"Wing-Hang Lo","sequence":"additional","affiliation":[]},{"family":"Yu-Liang Wu","sequence":"additional","affiliation":[]},{"family":"Shih-Chieh Chang","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"crossref","first-page":"68","DOI":"10.1109\/FPGA.1995.241947","article-title":"simultaneous depth and area minimization in lut-based fpga mapping","author":"cong","year":"1995","journal-title":"Third International ACM Symposium on Field-Programmable Gate Arrays"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580040"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1995.480198"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1145\/368122.368880"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.812369"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/54.156154"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114927"},{"key":"10","first-page":"606","article-title":"single-pass redundancy addition and removal","author":"chang","year":"2001","journal-title":"ICCAD"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/12.795224"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.569641"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/43.391740"},{"key":"4","doi-asserted-by":"crossref","first-page":"48","DOI":"10.1145\/360276.360298","article-title":"simultaneous logic decomposition with technologymapping in fpga designs","author":"chen","year":"2001","journal-title":"FPGA"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2000.912962"},{"key":"8","first-page":"268","article-title":"a fast graph-based alternative wiring scheme for boolean networks","author":"wu","year":"2000","journal-title":"Proceedings of the International Conference on VLSI Design"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01465920.pdf?arnumber=1465920","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,28]],"date-time":"2024-01-28T05:06:40Z","timestamp":1706418400000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1465920\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1465920","relation":{},"subject":[]}}