{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:04:49Z","timestamp":1730271889915,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2005.1466059","type":"proceedings-article","created":{"date-parts":[[2005,7,27]],"date-time":"2005-07-27T13:52:28Z","timestamp":1122472348000},"page":"6210-6213","source":"Crossref","is-referenced-by-count":1,"title":["Rapid and Precise Instruction Set Evaluation for Application Specific Processor Design"],"prefix":"10.1109","author":[{"given":"M.","family":"Masuda","sequence":"first","affiliation":[]},{"given":"K.","family":"Ito","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","first-page":"61","article-title":"rapid prototyping of complex instructions for embedded processors using peas-iii","author":"sasaki","year":"2000","journal-title":"Proc SASIMI 2000"},{"key":"2","first-page":"851","article-title":"processor generation method for pipelined processors in consideration with pipeline hazards","volume":"41","author":"itoh","year":"2000","journal-title":"IPSJ Journal"},{"key":"1","first-page":"1373","article-title":"satsuki: an integrated processor synthesis and compiler generation system","volume":"e79 d","author":"shackleford","year":"1996","journal-title":"IEICE Trans Inf & Syst"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/5.52214"},{"key":"6","first-page":"393","article-title":"instruction selection using binate covering for code size optimization","author":"liao","year":"1995","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1173051"},{"key":"4","first-page":"71","article-title":"a code generation method for datapath oriented application specific processor design","author":"ishiura","year":"2000","journal-title":"Proc SASIMI 2000"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1989.266596"},{"year":"0","key":"8"}],"event":{"name":"2005 IEEE International Symposium on Circuits and Systems","location":"Kobe, Japan"},"container-title":["2005 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9898\/31469\/01466059.pdf?arnumber=1466059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T21:41:09Z","timestamp":1489527669000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1466059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/iscas.2005.1466059","relation":{},"subject":[]}}