{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T16:53:20Z","timestamp":1729616000696,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2006.1692631","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T17:01:13Z","timestamp":1158944473000},"page":"4","source":"Crossref","is-referenced-by-count":0,"title":["Coupling aware RLC-based clock routings for crosstalk minimization"],"prefix":"10.1109","author":[{"family":"Chia-Chun Tsai","sequence":"first","affiliation":[]},{"family":"Jan-Ou Wu","sequence":"additional","affiliation":[]},{"family":"Chien-Wen Kao","sequence":"additional","affiliation":[]},{"family":"Trong-Yen Lee","sequence":"additional","affiliation":[]},{"family":"Rong-Shue Hsiao","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/DAC.1999.781281"},{"key":"2","first-page":"581","article-title":"Crosstalk-constrained performance optimization by using wire sizing and perturbation","author":"pan","year":"2000","journal-title":"International Conference on Computer Design"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/TVLSI.2002.808426"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/SOC.2003.1241502"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/DAC.1999.782048"},{"key":"6","first-page":"441","article-title":"A bus delay reduction technique considering crosstalk","author":"hirose","year":"2000","journal-title":"Design Automation and Test in Europe Conference and Exhibition"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/MWSCAS.2002.1187179"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/ICCAD.1993.580163"},{"key":"9","doi-asserted-by":"crossref","first-page":"1501","DOI":"10.1109\/TED.2003.813345","article-title":"A unified RLC model for high-speed onchip interconnects","volume":"50","author":"sim","year":"2003","journal-title":"IEEE Transactions on Electron Devices"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ASIC.2000.880770"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/TVLSI.2003.820529"},{"key":"12","first-page":"573","article-title":"Clock routing for high performance ICs","author":"jackson","year":"1999","journal-title":"Proc ACM\/IEEE Design Automation Conference"}],"event":{"acronym":"ISCAS-06","name":"2006 IEEE International Symposium on Circuits and Systems","location":"Island of Kos, Greece"},"container-title":["2006 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11145\/35661\/01692631.pdf?arnumber=1692631","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T09:30:33Z","timestamp":1497691833000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1692631\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2006.1692631","relation":{},"subject":[]}}