{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T21:37:17Z","timestamp":1729633037447,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2006.1693233","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T17:01:13Z","timestamp":1158944473000},"page":"2909-2912","source":"Crossref","is-referenced-by-count":9,"title":["Side Channel Analysis Resistant Design Flow"],"prefix":"10.1109","author":[{"given":"M.","family":"Aigner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Mangard","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F.","family":"Menichelli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Menicocci","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Olivieri","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Popp","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Scotti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Trifiletti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2005.4633506"},{"key":"11","first-page":"137","article-title":"Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology","volume":"2779","author":"tiri","year":"2003","journal-title":"Lecture Notes in Computer Science"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1007\/11545262_12","article-title":"Successfully Attacking Masked AES Hardware Implementations","author":"mangard","year":"2005","journal-title":"Lecture Notes in Computer Science (LNCS"},{"article-title":"Rechenwerk, Verfahren zum Ausfuhren einer Operation mit einem verschlu?sselten Operanden, Carry-Select-Addierer und Kryptographieprozessor","year":"2002","author":"klug","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268856"},{"year":"0","key":"1"},{"volume":"197","journal-title":"Advanced Encryption Standard FIPS","year":"0","key":"10"},{"key":"7","first-page":"546","article-title":"Power-Analysis Attack on an ASIC AES implementation","volume":"2","author":"berna ors","year":"0","journal-title":"ITCC '04 Proc of the Int Conf on Inf Technology Coding and Computing"},{"key":"6","first-page":"173","article-title":"Virtual Analysis and Reduction of Side-Channel Vulnerabilities of Smartcards","author":"den hartog","year":"2004","journal-title":"Proc of the 3rd International Workshop on Formal Aspects in Security and Trust"},{"key":"5","doi-asserted-by":"crossref","DOI":"10.1007\/11545262_13","article-title":"Masked Dual-Rail Pre-Charge Logic: DPA-Resistance without Routing Constraints","author":"popp","year":"2005","journal-title":"Lecture Notes in Computer Science (LNCS"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-30574-3_24","article-title":"Side-Channel Leakage of Masked CMOS Gates","author":"mangard","year":"2005","journal-title":"Lecture Notes in Computer Science (LNCS"},{"key":"9","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1007\/11545262_21","article-title":"Security Evaluation Against Electromagnetic Analysis at Design Time, Workshop on Cryptographic Hardware and Embedded Systems - CHES 2005","volume":"3659","author":"li","year":"2005","journal-title":"Lecture Notes in Computer Science"},{"key":"8","doi-asserted-by":"crossref","first-page":"481","DOI":"10.1007\/978-3-540-30205-6_50","article-title":"A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processor, Integrated Circuit and System Design - Power and Timing Modeling, Optimization and Simulation - PATMOS 2004","volume":"3254","author":"bucci","year":"2004","journal-title":"Lecture Notes in Computer Science"}],"event":{"name":"2006 IEEE International Symposium on Circuits and Systems","acronym":"ISCAS-06","location":"Island of Kos, Greece"},"container-title":["2006 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11145\/35661\/01693233.pdf?arnumber=1693233","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T09:30:43Z","timestamp":1497691843000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1693233\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2006.1693233","relation":{},"subject":[]}}