{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:27:48Z","timestamp":1747805268442},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iscas.2006.1693546","type":"proceedings-article","created":{"date-parts":[[2006,9,22]],"date-time":"2006-09-22T17:01:13Z","timestamp":1158944473000},"page":"4","source":"Crossref","is-referenced-by-count":2,"title":["Network-on-chip link analysis under power and performance constraints"],"prefix":"10.1109","author":[{"family":"Manho Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Daewook Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.E.","family":"Sobelman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.812104"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206364"},{"journal-title":"Predictive Technology Model (PTM)","year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2003.1219148"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2004.1274003"},{"key":"3","doi-asserted-by":"crossref","first-page":"33","DOI":"10.1145\/500001.500009","article-title":"powering networks on chips","author":"benini","year":"2001","journal-title":"International Symposium on System Synthesis (IEEE Cat No 01EX526) ISSS-01"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"1","first-page":"448","article-title":"SILENT: Serialized low energy transmission coding for on-chip interconnection networks","author":"lee","year":"2004","journal-title":"IEEE\/ACM International Conference on Computer Aided Design"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.2001.924555"},{"year":"0","key":"7"},{"article-title":"Interconnect modeling and optimization in deep sub-micron technologies","year":"2002","author":"sotiriadis","key":"6"},{"journal-title":"Circuits Interconnections and Packaging for VLSI","year":"1990","author":"bakoglou","key":"5"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"2002","author":"rabaey","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/APCCAS.2004.1412711"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/966747.966761"}],"event":{"name":"2006 IEEE International Symposium on Circuits and Systems","acronym":"ISCAS-06","location":"Island of Kos, Greece"},"container-title":["2006 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/11145\/35661\/01693546.pdf?arnumber=1693546","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T09:30:46Z","timestamp":1497691846000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1693546\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas.2006.1693546","relation":{},"subject":[]}}