{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,31]],"date-time":"2025-10-31T23:04:17Z","timestamp":1761951857750,"version":"build-2065373602"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4541435","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T16:26:17Z","timestamp":1213633577000},"page":"384-387","source":"Crossref","is-referenced-by-count":13,"title":["Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies"],"prefix":"10.1109","author":[{"given":"S.","family":"Mukhopadhyay","sequence":"first","affiliation":[{"name":"ECE Dept, Georgia Institute of Technology, Atlanta, USA"}]},{"given":"R.","family":"Rao","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA"}]},{"given":"J. J.","family":"Kim","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA"}]},{"given":"C. T.","family":"Chuang","sequence":"additional","affiliation":[{"name":"IBM T. J. Watson Research Center, Yorktown Heights, NY, USA"}]}],"member":"263","reference":[{"article-title":"memory device using a reduced word line voltage during read operations and a methof of accessing such a memory device","year":"0","author":"horne","key":"3"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.852295"},{"key":"1","first-page":"658","volume":"36","author":"bhavnagarwala","year":"2001","journal-title":"The impact of intrinsic device fluctuations on CMOS SRAM cellstability"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146930"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2006.1705290"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2005.1494075"},{"article-title":"vdd modulated sram for highly scaled, high performance cache","year":"0","author":"chappell","key":"4"},{"year":"0","key":"9"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2006.284405"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2008,5,18]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04541435.pdf?arnumber=4541435","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,16]],"date-time":"2024-02-16T01:22:46Z","timestamp":1708046566000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4541435\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4541435","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}