{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,1]],"date-time":"2025-11-01T21:32:43Z","timestamp":1762032763350},"reference-count":11,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4541484","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T16:26:17Z","timestamp":1213633577000},"page":"580-583","source":"Crossref","is-referenced-by-count":2,"title":["A Dual-Vt low leakage SRAM array robust to process variations"],"prefix":"10.1109","author":[{"family":"Jungseob Lee","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Lin Xie","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Azadeh","family":"Davoodi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Wisconsin at Madison, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"analysis of process variation's effect on sram's read stability","author":"tsai","year":"2006","journal-title":"ISQED"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIR.2004.1356657"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382534"},{"key":"1","article-title":"low-leakage sram design with dual v t transistors","author":"amelifard","year":"2006","journal-title":"ISQED"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.842846"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.820873"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.377982"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.122"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.134"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1145\/566408.566422"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.820648"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2008,5,18]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04541484.pdf?arnumber=4541484","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,16]],"date-time":"2024-02-16T01:23:26Z","timestamp":1708046606000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4541484\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4541484","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}