{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,1]],"date-time":"2026-01-01T10:10:57Z","timestamp":1767262257633},"reference-count":12,"publisher":"IEEE","license":[{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2008,5,1]],"date-time":"2008-05-01T00:00:00Z","timestamp":1209600000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4541789","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T16:26:17Z","timestamp":1213633577000},"source":"Crossref","is-referenced-by-count":4,"title":["ILP-based optimization of time-multiplexed I\/O assignment for multi-FPGA systems"],"prefix":"10.1109","author":[{"family":"Masato Inagi","sequence":"first","affiliation":[{"name":"Faculty of Environmental Engineering, The University of Kitakyushu, 1-1 Hibikino, Wakamatsu-ku, Fukuoka, 808-0135, JAPAN"}]},{"family":"Yasuhiro Takashima","sequence":"additional","affiliation":[{"name":"Faculty of Environmental Engineering, The University of Kitakyushu, 1-1 Hibikino, Wakamatsu-ku, Fukuoka, 808-0135, JAPAN"}]},{"family":"Yuichi Nakamura","sequence":"additional","affiliation":[{"name":"System IP Core Laboratories, NEC Corporation, 1753 Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa, 211-8666, JAPAN"}]},{"family":"Atsushi Takahashi","sequence":"additional","affiliation":[{"name":"Dept. of Comms. and Integrated Systems, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, 152-8550, JAPAN"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1989.100747"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1982.1585498"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.829812"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1970.tb01770.x"},{"key":"7","article-title":"combinatorial optimization","author":"cook","year":"1998","journal-title":"John Willy & Sons Inc"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/43.640619"},{"key":"5","first-page":"194","article-title":"vlsi circuit partitioning by cluster-removal using iterative improvement techniques","author":"dutt","year":"1996","journal-title":"Proc IEEE ICCAD96"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1993.279469"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/504914.504918"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/92.748202"},{"key":"11","year":"0"},{"key":"12","year":"0"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Seattle, WA, USA","start":{"date-parts":[[2008,5,18]]},"end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04541789.pdf?arnumber=4541789","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,16]],"date-time":"2024-02-16T01:23:14Z","timestamp":1708046594000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4541789\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4541789","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}