{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T15:49:21Z","timestamp":1725724161000},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4542029","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T12:26:17Z","timestamp":1213619177000},"page":"2761-2764","source":"Crossref","is-referenced-by-count":3,"title":["On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits"],"prefix":"10.1109","author":[{"given":"A.","family":"Sathanur","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Calimera","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Pullini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Benini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Macii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Macii","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Poncino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/ICCD.2005.34"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/JPROC.2002.808156"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1093\/ietele\/e88-c.4.509"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/DATE.2007.364520"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1145\/1283780.1283803"},{"key":"4","first-page":"113","article-title":"challenges in sleep transistor design and implementation in low-power designs","author":"shi","year":"2007","journal-title":"DAC-06"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008","start":{"date-parts":[[2008,5,18]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04542029.pdf?arnumber=4542029","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T10:40:37Z","timestamp":1489660837000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4542029\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4542029","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}