{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:46:23Z","timestamp":1759146383418,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2008,5]]},"DOI":"10.1109\/iscas.2008.4542198","type":"proceedings-article","created":{"date-parts":[[2008,6,16]],"date-time":"2008-06-16T12:26:17Z","timestamp":1213619177000},"page":"3438-3441","source":"Crossref","is-referenced-by-count":1,"title":["Improving datapath utilization of programmable DSP with composite functional units"],"prefix":"10.1109","author":[{"family":"Shih-Hao Ou","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yi Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Tay-Jyi Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chih-Wei Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","article-title":"a unified risc\/vliw dsp core for multimedia processing","volume":"2","author":"lin","year":"2005","journal-title":"Technology in Society"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2003.1213417"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206291"},{"journal-title":"Computer Architecture - A Quantitative Approach","year":"2002","author":"hennessy","key":"1"},{"key":"7","article-title":"organizing pattern libraries for asip design","author":"dittmann","year":"2003","journal-title":"IBM Research Report"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/106972.107003"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2000.824366"},{"key":"4","article-title":"overcoming the limitations of conventional vector processors","author":"kozyrakis","year":"2003","journal-title":"Proc ISCA"},{"key":"9","article-title":"area-efficient register organization for fully-synthesizable vliw dsp cores","author":"lin","year":"2006","journal-title":"International Journal of Electrical Engineering"},{"journal-title":"VLSI Digital Signal Processing Systems - Design and Implementation","year":"1999","author":"parhi","key":"8"}],"event":{"name":"2008 IEEE International Symposium on Circuits and Systems - ISCAS 2008","start":{"date-parts":[[2008,5,18]]},"location":"Seattle, WA, USA","end":{"date-parts":[[2008,5,21]]}},"container-title":["2008 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4534149\/4541329\/04542198.pdf?arnumber=4542198","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T10:44:44Z","timestamp":1489661084000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4542198\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2008.4542198","relation":{},"subject":[],"published":{"date-parts":[[2008,5]]}}}