{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,3]],"date-time":"2025-08-03T04:03:00Z","timestamp":1754193780855,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,5]]},"DOI":"10.1109\/iscas.2009.5118221","type":"proceedings-article","created":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T14:59:27Z","timestamp":1246460367000},"page":"2149-2152","source":"Crossref","is-referenced-by-count":39,"title":["A switched capacitor implementation of the generalized linear integrate-and-fire neuron"],"prefix":"10.1109","author":[{"given":"Fopefolu","family":"Folowosele","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andre","family":"Harrison","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andrew","family":"Cassidy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andreas G.","family":"Andreou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ralph","family":"Etienne-Cummings","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Mihalas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ernst","family":"Niebur","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tara Julia","family":"Hamilton","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/S0006-3495(67)86574-3"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2006.883007"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2004.832719"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2008.02-07-466"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/4.92015"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2003.1206342"},{"key":"ref6","first-page":"744","article-title":"Low power real time electronic neuron vlsi design using subthreshold technique","volume":"4","author":"jun","year":"2004","journal-title":"IEEE ISCAS"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1142\/S0129065706000846"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2007.12.037"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TNN.2003.820440"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1049\/el:19950932"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1162\/neco.2008.12-07-680"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1098\/rspb.1936.0012"}],"event":{"name":"2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009","start":{"date-parts":[[2009,5,24]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2009,5,27]]}},"container-title":["2009 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5076158\/5117665\/05118221.pdf?arnumber=5118221","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T17:43:55Z","timestamp":1489772635000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5118221\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2009.5118221","relation":{},"subject":[],"published":{"date-parts":[[2009,5]]}}}