{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:12:15Z","timestamp":1729671135236,"version":"3.28.0"},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,5]]},"DOI":"10.1109\/iscas.2009.5118367","type":"proceedings-article","created":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T10:59:27Z","timestamp":1246445967000},"page":"2733-2736","source":"Crossref","is-referenced-by-count":1,"title":["Efficient test circuit to qualify logic cells"],"prefix":"10.1109","author":[{"given":"R. P.","family":"Ribas","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Bavaresco","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Lubaszewski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A. I.","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","first-page":"173","article-title":"benchmark circuits improve the quality of a standard cell library","author":"lin","year":"1999","journal-title":"Proc Asia and South Pacific Design Automation Conf (ASP-DAC)"},{"article-title":"optimization of circuit designs using a continuous spectrum of library cells","year":"2003","author":"de dood","key":"2"},{"key":"10","doi-asserted-by":"crossref","first-page":"1072","DOI":"10.1109\/T-ED.1984.21663","article-title":"test structures for propagation delay measurements on high-speed integrated circuits","volume":"31","author":"long","year":"1984","journal-title":"IEEE Transactions on Electron Devices"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.74"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2003.1232251"},{"article-title":"library test circuit and library test method","year":"2007","author":"salgunan","key":"6"},{"article-title":"system and method for designing, fabricating and testing multiple cell test structures to validate a cell library","year":"1998","author":"heavlin","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1990.186174"},{"key":"9","first-page":"370","article-title":"nbti-aware synthesis of digital circuits","author":"kumar","year":"2007","journal-title":"Design Automation Conf"},{"year":"0","key":"8"},{"year":"0","key":"11"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297715"}],"event":{"name":"2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009","start":{"date-parts":[[2009,5,24]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2009,5,27]]}},"container-title":["2009 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5076158\/5117665\/05118367.pdf?arnumber=5118367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T17:29:01Z","timestamp":1497806941000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5118367\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2009.5118367","relation":{},"subject":[],"published":{"date-parts":[[2009,5]]}}}