{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:34:52Z","timestamp":1725399292646},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2009,5]]},"DOI":"10.1109\/iscas.2009.5118461","type":"proceedings-article","created":{"date-parts":[[2009,7,1]],"date-time":"2009-07-01T10:59:27Z","timestamp":1246445967000},"page":"3110-3113","source":"Crossref","is-referenced-by-count":1,"title":["On-chip principal component analysis with a mean pre-estimation method for spike sorting"],"prefix":"10.1109","author":[{"given":"Tung-Chien","family":"Chen","sequence":"first","affiliation":[]},{"given":"Kuanfu","family":"Chen","sequence":"additional","affiliation":[]},{"family":"Wentai Liu","sequence":"additional","affiliation":[]},{"given":"Liang-Gee","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"g-lab\/software","year":"0","author":"quian quiroga","key":"13"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001877"},{"key":"12","article-title":"neusort2.0: a multiple-channel neural signal processor with systolic array buffer and channel-interleaving processing schedule","author":"chen","year":"0","journal-title":"to appear Proc of IEEE conferenc on Engineering in Medicine and Biology Society"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/MSP.2008.4408439"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1977.10559"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TNSRE.2005.854307"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2008.4523099"},{"key":"7","article-title":"vlsi architecture of leading eigenvector generation for on-chip principal component analysis spike sorting system","author":"chen","year":"0","journal-title":"to appear Proc of IEEE conferenc on Engineering in Medicine and Biology Society"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/IEMBS.2006.260912"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1016\/S0165-0270(02)00032-8"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1016\/S0165-0270(00)00250-8"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/10.871415"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1016\/j.patrec.2007.01.012"}],"event":{"name":"2009 IEEE International Symposium on Circuits and Systems - ISCAS 2009","start":{"date-parts":[[2009,5,24]]},"location":"Taipei, Taiwan","end":{"date-parts":[[2009,5,27]]}},"container-title":["2009 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5076158\/5117665\/05118461.pdf?arnumber=5118461","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,17]],"date-time":"2017-03-17T13:20:48Z","timestamp":1489756848000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5118461\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2009.5118461","relation":{},"subject":[],"published":{"date-parts":[[2009,5]]}}}