{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,16]],"date-time":"2026-10-16T05:47:22Z","timestamp":1792129642732,"version":"4.4.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/iscas.2010.5536970","type":"proceedings-article","created":{"date-parts":[[2010,8,9]],"date-time":"2010-08-09T18:13:20Z","timestamp":1281377600000},"page":"1947-1950","source":"Crossref","is-referenced-by-count":540,"title":["A wafer-scale neuromorphic hardware system for large-scale neural modeling"],"prefix":"10.1109","author":[{"given":"Johannes","family":"Schemmel","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Daniel","family":"Briiderle","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andreas","family":"Griibl","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Matthias","family":"Hock","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Karlheinz","family":"Meier","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sebastian","family":"Millner","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.3390\/s8095352"},{"key":"ref3","year":"2007","journal-title":"ITRS &#x201C;International technology roadmap for semiconductors"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73916-6"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1162\/neco.1997.9.3.503"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.3389\/neuro.11.017.2009"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1152\/jn.00686.2005"},{"key":"ref8","article-title":"Implementing synaptic plasticity in a VLSI spiking neural network model","author":"schemmel","year":"0","journal-title":"Proceedings of the 2006 International Joint Conference on Neural Networks (IJCNN'06)"},{"key":"ref7","article-title":"Modeling synaptic plasticity within networks of highly accelerated I&F neu-rons","author":"schemmel","year":"0","journal-title":"Proceedings of the 2007 IEEE International Symposium on Circuits and Systems (ISCAS'07)"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/0893-6080(88)90024-X"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.2008.4633828"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.neunet.2006.05.029"}],"event":{"name":"2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010","location":"Paris, France","start":{"date-parts":[[2010,5,30]]},"end":{"date-parts":[[2010,6,2]]}},"container-title":["Proceedings of 2010 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5512009\/5536941\/05536970.pdf?arnumber=5536970","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T18:40:16Z","timestamp":1489862416000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5536970\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2010.5536970","relation":{},"subject":[],"published":{"date-parts":[[2010,5]]}}}