{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T13:47:51Z","timestamp":1725630471483},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/iscas.2010.5537703","type":"proceedings-article","created":{"date-parts":[[2010,8,9]],"date-time":"2010-08-09T18:13:20Z","timestamp":1281377600000},"page":"3861-3864","source":"Crossref","is-referenced-by-count":1,"title":["A 7.7mW\/1.0ns\/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface"],"prefix":"10.1109","author":[{"given":"Hyun-Woo","family":"Lee","sequence":"first","affiliation":[]},{"given":"Yong-Hoon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Won-Joo","family":"Yun","sequence":"additional","affiliation":[]},{"given":"Eun Young","family":"Park","sequence":"additional","affiliation":[]},{"given":"Kang Youl","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Jaeil","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Kwang Hyun","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jong Ho","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Kyung Whan","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Nam Gyu","family":"Rye","sequence":"additional","affiliation":[]},{"given":"Kwan-Weon","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Jun Hyun","family":"Chun","sequence":"additional","affiliation":[]},{"given":"Chulwoo","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Young-Jung","family":"Choi","sequence":"additional","affiliation":[]},{"given":"Byong-Tae","family":"Chung","sequence":"additional","affiliation":[]},{"given":"Joong Sik","family":"Kih","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"283","article-title":"A low cost high performance Register-Controlled digital DLL for 1Gbps x32 DDR SDRAM","author":"kwak","year":"0","journal-title":"Symp Circuits Dig Tech Papers"},{"key":"ref3","first-page":"68","article-title":"Digitally controlled DLL and I\/O circuits for 500Mb\/s\/pin x16 DDR SDRAM","author":"lee","year":"0","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2008.4708773"},{"key":"ref6","first-page":"160","article-title":"A 2.5Gb\/s\/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL","author":"lee","year":"0","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref11","first-page":"140","article-title":"An 1.6V 3.3Gbps Dual-Mode Phase and Delay Locked Loop using power noise management technique with unregulated power supply for pseudo-rank DRAM in 54nm CMOS technology","author":"lee","year":"2009","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2005.251750"},{"key":"ref8","first-page":"282","article-title":"A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology","author":"yun","year":"0","journal-title":"ISSCC Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2006.357916"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2000.852847"},{"key":"ref9","first-page":"245","article-title":"A Single-Loop DLL Using an OR-AND Duty-Cycle Correction Technique","author":"song","year":"0","journal-title":"ASSCC Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.760373"}],"event":{"name":"2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010","start":{"date-parts":[[2010,5,30]]},"location":"Paris, France","end":{"date-parts":[[2010,6,2]]}},"container-title":["Proceedings of 2010 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5512009\/5536941\/05537703.pdf?arnumber=5537703","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,19]],"date-time":"2017-03-19T01:49:29Z","timestamp":1489888169000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5537703\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2010.5537703","relation":{},"subject":[],"published":{"date-parts":[[2010,5]]}}}