{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T23:41:42Z","timestamp":1725406902539},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,5]]},"DOI":"10.1109\/iscas.2010.5537773","type":"proceedings-article","created":{"date-parts":[[2010,8,9]],"date-time":"2010-08-09T22:13:20Z","timestamp":1281392000000},"page":"3665-3668","source":"Crossref","is-referenced-by-count":0,"title":["Scaling analysis of yield optimization considering supply and threshold voltage variations"],"prefix":"10.1109","author":[{"given":"Kian","family":"Haghdad","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mohab","family":"Anis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.883926"},{"journal-title":"(PTM)","year":"0","key":"ref11"},{"key":"ref12","first-page":"169","article-title":"A Fast Lithography Verification Framework for Litho-Friendly Layout Design","author":"ban","year":"2005","journal-title":"ISQED'05"},{"journal-title":"Calibre LFD Litho-Friendly Design","year":"0","author":"graphics","key":"ref13"},{"key":"ref14","first-page":"285","article-title":"Yield optimization with energy-delay constraints in low power dig-ital circuits","author":"cao","year":"2003","journal-title":"IEEE Conference on Electron Devices and Solid-State Circuits"},{"key":"ref4","article-title":"Managing Process Variation in Intels 45nm CMOS Technology","author":"kuhn","year":"2008","journal-title":"Intel Technology Journal"},{"key":"ref3","first-page":"535","article-title":"Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance","author":"srivastava","year":"0","journal-title":"Proc DAC 2005"},{"year":"2005","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.2003288"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EDSSC.2007.4450067"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1063803.1063805"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.898625"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2006.889370"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373463"}],"event":{"name":"2010 IEEE International Symposium on Circuits and Systems - ISCAS 2010","start":{"date-parts":[[2010,5,30]]},"location":"Paris, France","end":{"date-parts":[[2010,6,2]]}},"container-title":["Proceedings of 2010 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5512009\/5536941\/05537773.pdf?arnumber=5537773","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,18]],"date-time":"2017-03-18T23:01:17Z","timestamp":1489878077000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5537773\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,5]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas.2010.5537773","relation":{},"subject":[],"published":{"date-parts":[[2010,5]]}}}