{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:10:35Z","timestamp":1730272235863,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/iscas.2011.5937530","type":"proceedings-article","created":{"date-parts":[[2011,7,7]],"date-time":"2011-07-07T13:30:57Z","timestamp":1310045457000},"page":"177-180","source":"Crossref","is-referenced-by-count":0,"title":["Design of high-speed clock recovery circuit for burst-mode applications"],"prefix":"10.1109","author":[{"given":"Soojin","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kyeongsoon","family":"Cho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2006.382156"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2002.804342"},{"key":"ref10","first-page":"526","article-title":"A 2.5Gb\/s, Low Power Clock and Data Recovery Circuit","author":"du","year":"2007","journal-title":"IEEE Canadian Conference on Electrical and Computer Engineering"},{"key":"ref6","first-page":"1","article-title":"A 2&#x2013;5Gb\/s Fully Differential 3X Oversampling CDR for High-speed Serial Data Link","author":"kiddimapillai","year":"2009","journal-title":"IEEE Norchip Conference"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2019079"},{"key":"ref5","first-page":"198","article-title":"A Portable Clock Recovery Circuit(CRC) for System-on-chip Serial Data Communication","author":"muhamman","year":"2006","journal-title":"IEEE International Conference on Microelectronics"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.875292"},{"key":"ref7","first-page":"1170","article-title":"An All-digital Clock Recovery and Data Timing Circuitry for High Speed NRZ Data Communications","author":"muhammad","year":"2002","journal-title":"IEICE Trans on ELECTRON"},{"key":"ref2","first-page":"143","article-title":"A 2.5&#x2013;3.125Gbps Quad Transceiver with Second Order Analog DLL based CDRs","volume":"40","author":"coban","year":"2005","journal-title":"IEEE Jounal of Solid-State Circuits"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICSPC.2007.4728475"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.824704"}],"event":{"name":"2011 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2011,5,15]]},"location":"Rio de Janeiro, Brazil","end":{"date-parts":[[2011,5,18]]}},"container-title":["2011 IEEE International Symposium of Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5910713\/5937406\/05937530.pdf?arnumber=5937530","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T03:41:13Z","timestamp":1490067673000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5937530\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2011.5937530","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}