{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:10:51Z","timestamp":1730272251330,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/iscas.2011.5937607","type":"proceedings-article","created":{"date-parts":[[2011,7,7]],"date-time":"2011-07-07T17:30:57Z","timestamp":1310059857000},"page":"482-485","source":"Crossref","is-referenced-by-count":3,"title":["A new frequency synthesizers stabilization method based on a mixed Phase Locked Loop and Delay Locked Loop architecture"],"prefix":"10.1109","author":[{"given":"P.O.","family":"Lucas de Peslouan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Majek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Taris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Y.","family":"Deval","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Belot","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.B.","family":"Begueret","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2006.320953"},{"key":"ref11","first-page":"798","article-title":"A wide-range DLL-based clock generator with phase error calibration","author":"cheng","year":"2008","journal-title":"IEEE International Conference on Electronics Circuits and Systems"},{"key":"ref12","first-page":"788","article-title":"A mixed PLL\/DLL architecture for low jitter clock generation","volume":"4","author":"bae","year":"2004","journal-title":"Proceedings of the 2004 International Symposium on Circuits and Systems"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2005.843505"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/775832.775855"},{"key":"ref6","first-page":"545","article-title":"A Performance Comparaison of PLLs for Clock Generation using Ring Oscillator VCO and LC oscillator in a Digital CMOS Process","author":"miyazaki","year":"2004","journal-title":"Asia and South Pacific Design Automation Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2003.819114"},{"key":"ref8","first-page":"247","author":"razavi","year":"1998","journal-title":"RF Microelectronics"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/4.987085"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISIE.2004.1571804"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/RME.2007.4401843"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.919512"}],"event":{"name":"2011 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2011,5,15]]},"location":"Rio de Janeiro, Brazil","end":{"date-parts":[[2011,5,18]]}},"container-title":["2011 IEEE International Symposium of Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5910713\/5937406\/05937607.pdf?arnumber=5937607","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T09:43:55Z","timestamp":1490089435000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5937607\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2011.5937607","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}