{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:01:35Z","timestamp":1761580895655},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/iscas.2011.5937928","type":"proceedings-article","created":{"date-parts":[[2011,7,7]],"date-time":"2011-07-07T13:30:57Z","timestamp":1310045457000},"page":"1776-1779","source":"Crossref","is-referenced-by-count":34,"title":["Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes"],"prefix":"10.1109","author":[{"given":"Yang","family":"Sun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guohui","family":"Wang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Joseph R.","family":"Cavallaro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICC.2007.750"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/GLOCOM.2007.620"},{"key":"ref10","first-page":"211","article-title":"A 4.84 mm2 847C955 Mb\/s 397 mW dual-path fully-overlapped QC-LDPC decoder for the WiMAX system in 0.13 urn CMOS","author":"xiang","year":"2010","journal-title":"IEEE Symposium on VLSI Circuits"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ACSSC.2008.5074592"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378514"},{"key":"ref8","first-page":"1","article-title":"A Parallel Layered Decoding Algorithm for LDPC Codes in WiMax System","author":"jun","year":"2009","journal-title":"IEEE WiCom"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSAC.2009.090816"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817545"},{"key":"ref9","first-page":"582","article-title":"High-Throughput Layered LDPC Decoding Architecture","author":"cui","year":"2009","journal-title":"IEEE Tran VLSI"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SIPS.2004.1363033"}],"event":{"name":"2011 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2011,5,15]]},"location":"Rio de Janeiro, Brazil","end":{"date-parts":[[2011,5,18]]}},"container-title":["2011 IEEE International Symposium of Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5910713\/5937406\/05937928.pdf?arnumber=5937928","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:37:19Z","timestamp":1490078239000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5937928\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2011.5937928","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}