{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T01:09:27Z","timestamp":1725412167009},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,5]]},"DOI":"10.1109\/iscas.2011.5937969","type":"proceedings-article","created":{"date-parts":[[2011,7,7]],"date-time":"2011-07-07T13:30:57Z","timestamp":1310045457000},"page":"1940-1943","source":"Crossref","is-referenced-by-count":1,"title":["Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits"],"prefix":"10.1109","author":[{"given":"Jianchao","family":"Lu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Baris","family":"Taskin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2010.62"},{"journal-title":"Synopsys 90nm Generic Library Synopsys Inc","year":"2009","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.1998.669513"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/277044.277128"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065629"},{"key":"ref3","first-page":"376","article-title":"Skew aware polarity assignment in clock tree","author":"chen","year":"2007","journal-title":"Proceedings of the IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2008.4681608"},{"key":"ref5","first-page":"558","article-title":"Clock buffer polarity assignment for power noise reduction","author":"samanta","year":"2006","journal-title":"Proceedings of IEEE\/ACM International Conference on Computer-aided Design (ICCAD)"},{"key":"ref8","first-page":"765","article-title":"Clock buffer polarity assignment considering capacitive load","author":"lu","year":"2010","journal-title":"International Symposium on Quality Electronic Design (ISQED)"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630115"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/309847.310054"},{"journal-title":"Digital Integrated Circuits A Design Perspective","year":"2003","author":"rabaey","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/43.924824"}],"event":{"name":"2011 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2011,5,15]]},"location":"Rio de Janeiro, Brazil","end":{"date-parts":[[2011,5,18]]}},"container-title":["2011 IEEE International Symposium of Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5910713\/5937406\/05937969.pdf?arnumber=5937969","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,21]],"date-time":"2017-03-21T06:37:23Z","timestamp":1490078243000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5937969\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2011.5937969","relation":{},"subject":[],"published":{"date-parts":[[2011,5]]}}}