{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:12:51Z","timestamp":1730272371614,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/iscas.2012.6271574","type":"proceedings-article","created":{"date-parts":[[2012,8,22]],"date-time":"2012-08-22T16:02:44Z","timestamp":1345651364000},"page":"1652-1655","source":"Crossref","is-referenced-by-count":6,"title":["A chip-to-chip clock-deskewing circuit for 3-D ICs"],"prefix":"10.1109","author":[{"given":"Ai-Jia","family":"Chuang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ching-Yuan","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"crossref","first-page":"554","DOI":"10.1109\/4.753689","article-title":"Low-power clock-deskew buffer for high-speed digital circuits","volume":"34","author":"liu","year":"1999","journal-title":"IEEE J Solid-State Circuit"},{"journal-title":"Clock Deskewing Apparatus Including Three-input Phase Detector","year":"1997","author":"mcbride","key":"2"},{"journal-title":"Three-Dimensional Integrated Circuit Design","year":"2009","author":"pavlidis","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/PRIMEASIA.2009.5397388"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1049\/el:19930816"},{"key":"5","doi-asserted-by":"crossref","first-page":"266","DOI":"10.1109\/4.902767","article-title":"A one-wire approach for skewcompensating clock distribution based on bidirectional techniques","volume":"36","author":"yang","year":"2001","journal-title":"IEEE J Solid-State Circuit"},{"key":"4","first-page":"798","article-title":"Digital delay locked loop and design technique for highspeed synchronous interface","volume":"e97 c","author":"okajima","year":"1996","journal-title":"IEICE Trans Electron"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/4.68134"},{"journal-title":"A 65nm CMOS 150MHz-2GHz Wide Range PLL","year":"0","author":"tasi","key":"8"}],"event":{"name":"2012 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2012,5,20]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2012,5,23]]}},"container-title":["2012 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6257548\/6270389\/06271574.pdf?arnumber=6271574","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,8,11]],"date-time":"2021-08-11T20:38:55Z","timestamp":1628714335000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6271574\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/iscas.2012.6271574","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}