{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T10:46:24Z","timestamp":1725705984798},"reference-count":12,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/iscas.2012.6271840","type":"proceedings-article","created":{"date-parts":[[2012,8,22]],"date-time":"2012-08-22T16:02:44Z","timestamp":1345651364000},"page":"261-264","source":"Crossref","is-referenced-by-count":15,"title":["A power management architecture for fast per-core DVFS in heterogeneous MPSoCs"],"prefix":"10.1109","author":[{"given":"Sebastian","family":"Hoppner","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chenming","family":"Shao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Holger","family":"Eisenreich","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Georg","family":"Ellguth","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mario","family":"Ander","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rene","family":"Schuffny","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/JSSC.2011.2108121"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/DATE.2011.5763052"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1145\/1146909.1146943"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/MCAS.2009.935693"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/TVLSI.2010.2055907"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/ISSCC.2005.1493989"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/JSSC.2009.2013772"},{"key":"4","first-page":"123","article-title":"System level analysis of fast, per-core DVFS using on-chip switching regulators","author":"kim","year":"2008","journal-title":"High Performance Computer Architecture 2008 HPCA 2008 IEEE 14th International Symposium on"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/LPE.2003.1231828"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/ASPDAC.2005.1466478"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ISCAS.2008.4541648"},{"key":"12","article-title":"An open-loop clock generator for fast frequency scaling in 65nm CMOS technology","author":"ho?ppner","year":"2011","journal-title":"Mixed Design of Integrated Circuits Systems 2011"}],"event":{"name":"2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012","start":{"date-parts":[[2012,5,20]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2012,5,23]]}},"container-title":["2012 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6257548\/6270389\/06271840.pdf?arnumber=6271840","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T01:18:36Z","timestamp":1490145516000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6271840\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":12,"URL":"https:\/\/doi.org\/10.1109\/iscas.2012.6271840","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}