{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T22:14:56Z","timestamp":1725401696065},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2012,5]]},"DOI":"10.1109\/iscas.2012.6271851","type":"proceedings-article","created":{"date-parts":[[2012,8,22]],"date-time":"2012-08-22T16:02:44Z","timestamp":1345651364000},"page":"265-268","source":"Crossref","is-referenced-by-count":4,"title":["Two-level configuration for FPGA: A new design methodology based on a computing fabric"],"prefix":"10.1109","author":[{"given":"Mathieu","family":"Allard","sequence":"first","affiliation":[]},{"given":"Patrick","family":"Grogan","sequence":"additional","affiliation":[]},{"given":"Yvon","family":"Savaria","sequence":"additional","affiliation":[]},{"given":"Jean-Pierre","family":"David","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/ICCIT.2008.23"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.397"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2006.1649570"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON.2009.5351605"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/12.859540"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2007.31"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:20045086"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1049\/iet-ipr:20080057"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/NSSMIC.2004.1462492"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/PARELEC.2006.51"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/CIT.2010.54"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1145\/1132952.1132953"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.87"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.915390"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/43.898829"},{"key":"9","first-page":"105","article-title":"A network on chip architecture and design methodology","author":"kumar","year":"2002","journal-title":"VLSI 2002 Proceedings IEEE Computer Society Annual Symposium on"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.2008.4580150"}],"event":{"name":"2012 IEEE International Symposium on Circuits and Systems - ISCAS 2012","start":{"date-parts":[[2012,5,20]]},"location":"Seoul, Korea (South)","end":{"date-parts":[[2012,5,23]]}},"container-title":["2012 IEEE International Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6257548\/6270389\/06271851.pdf?arnumber=6271851","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T01:18:50Z","timestamp":1490145530000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6271851\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,5]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iscas.2012.6271851","relation":{},"subject":[],"published":{"date-parts":[[2012,5]]}}}