{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:20:49Z","timestamp":1725614449602},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/iscas.2013.6571965","type":"proceedings-article","created":{"date-parts":[[2013,8,14]],"date-time":"2013-08-14T15:40:23Z","timestamp":1376494823000},"page":"789-792","source":"Crossref","is-referenced-by-count":7,"title":["Logic-on-logic partitioning techniques for 3-dimensional integrated circuits"],"prefix":"10.1109","author":[{"given":"Gopi","family":"Neela","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeffrey","family":"Draper","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"13","DOI":"10.1016\/B978-0-12-374343-5.00005-8"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ASAP.2002.1030716"},{"key":"12","article-title":"Logical effort: Designing for speed on the back of an envelope","author":"sproull","year":"1991","journal-title":"IEEE Advanced Research in VLSI"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/MICRO.2006.18"},{"year":"0","key":"2"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1007\/978-1-4419-0962-6_4"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1016\/j.mejo.2009.03.004"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/MWSCAS.2012.6292061"},{"doi-asserted-by":"publisher","key":"6","DOI":"10.1109\/ISCAS.2006.1693742"},{"key":"5","first-page":"103","article-title":"Architecting microprocessor components in 3D design space","author":"vaidyanathan","year":"2007","journal-title":"VLSI Design 2007 Held Jointly with 6th International Conference on Embedded Systems 20th International Conference on"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/MM.2007.59"},{"year":"0","key":"9"},{"year":"0","key":"8"}],"event":{"name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2013,5,19]]},"location":"Beijing","end":{"date-parts":[[2013,5,23]]}},"container-title":["2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6560459\/6571764\/06571965.pdf?arnumber=6571965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,14]],"date-time":"2020-10-14T15:35:06Z","timestamp":1602689706000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/6571965"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2013.6571965","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}