{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,29]],"date-time":"2025-09-29T11:55:10Z","timestamp":1759146910963},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,5]]},"DOI":"10.1109\/iscas.2013.6572199","type":"proceedings-article","created":{"date-parts":[[2013,8,14]],"date-time":"2013-08-14T15:40:23Z","timestamp":1376494823000},"page":"1732-1735","source":"Crossref","is-referenced-by-count":2,"title":["Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis"],"prefix":"10.1109","author":[{"family":"Bo Huang","sequence":"first","affiliation":[]},{"family":"Song Chen","sequence":"additional","affiliation":[]},{"family":"Wei Zhong","sequence":"additional","affiliation":[]},{"given":"Takeshi","family":"Yoshimura","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937785"},{"key":"14","first-page":"517","article-title":"Application-specific 3d networkon-chip design using simulated allocation","author":"zhou","year":"2010","journal-title":"ASP-DAC 2010"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2009.5090625"},{"key":"12","doi-asserted-by":"crossref","DOI":"10.1109\/TVLSI.2006.871762","article-title":"Linear-programming-based techniques for synthesis of network-on-chip architectures","author":"srinivasan","year":"2006","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2010.04.001"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2008.917968"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2005.22"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1233501.1233573"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2091686"},{"key":"6","article-title":"Application-specific network-on-chip synthesis with topology-aware floorplanning","author":"huang","year":"2012","journal-title":"SBCCI"},{"key":"5","doi-asserted-by":"crossref","DOI":"10.1007\/BF02283688","article-title":"P.: Minimum concave-cost network flow problems: Applications, complexity, and algorithms","author":"guisewite","year":"1990","journal-title":"AOR"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2005.1466143"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2010.5419902"},{"key":"8","first-page":"541","article-title":"Is 3d integration an opportunity or just a hype?","author":"li","year":"2010","journal-title":"ASP-DAC"}],"event":{"name":"2013 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2013,5,19]]},"location":"Beijing","end":{"date-parts":[[2013,5,23]]}},"container-title":["2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6560459\/6571764\/06572199.pdf?arnumber=6572199","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,21]],"date-time":"2017-06-21T17:49:56Z","timestamp":1498067396000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6572199\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,5]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas.2013.6572199","relation":{},"subject":[],"published":{"date-parts":[[2013,5]]}}}