{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,1]],"date-time":"2025-10-01T16:22:24Z","timestamp":1759335744470,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/iscas.2014.6865088","type":"proceedings-article","created":{"date-parts":[[2014,7,30]],"date-time":"2014-07-30T17:16:29Z","timestamp":1406740589000},"page":"153-156","source":"Crossref","is-referenced-by-count":3,"title":["Synthesis of asynchronous QDI circuits using synchronous coding specifications"],"prefix":"10.1109","author":[{"given":"Rong","family":"Zhou","sequence":"first","affiliation":[]},{"given":"Kwen-Siong","family":"Chong","sequence":"additional","affiliation":[]},{"given":"Bah-Hwee","family":"Gwee","sequence":"additional","affiliation":[]},{"given":"Joseph S.","family":"Chang","sequence":"additional","affiliation":[]},{"given":"Weng-Geng","family":"Ho","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"3","DOI":"10.1007\/978-1-4757-3385-3"},{"doi-asserted-by":"publisher","key":"2","DOI":"10.1109\/JSSC.2007.903039"},{"doi-asserted-by":"publisher","key":"10","DOI":"10.1109\/MDT.2002.1018139"},{"key":"1","first-page":"573","article-title":"An ultra-low power asynchronous-logic in-situ self-adaptive vdd system for wireless sensor networks","volume":"48","author":"tong","year":"2013","journal-title":"IEEE JSSC"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/ASYNC.2000.836967"},{"key":"6","article-title":"Synthesis of asynchronous VLSI circuits","author":"martin","year":"1991","journal-title":"Technical Report California Institute of Technology"},{"year":"1985","author":"hoare","journal-title":"Communicating Sequential Processes","key":"5"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1109\/TCAD.2005.860958"},{"key":"9","first-page":"315","article-title":"Petrify: A tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"3","author":"cortadella","year":"1997","journal-title":"IEICE Transactions on Information and Systems"},{"key":"8","doi-asserted-by":"crossref","first-page":"682","DOI":"10.1109\/TVLSI.2009.2039501","article-title":"Modeling and synthesis of asynchronous pipelines","volume":"19","author":"chong-fatt","year":"2011","journal-title":"IEEE Trans VLSI"},{"key":"11","article-title":"A low overhead quasi-delay-insensitive (QDI) asynchronous data path synthesis based on microcell-interleaving genetic algorithm (MIGA)","author":"zhou","year":"0","journal-title":"IEEE Trans CAD-ICS"}],"event":{"name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2014,6,1]]},"location":"Melbourne VIC, Australia","end":{"date-parts":[[2014,6,5]]}},"container-title":["2014 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6852006\/6865048\/06865088.pdf?arnumber=6865088","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:37:36Z","timestamp":1498138656000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6865088\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2014.6865088","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}