{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T03:54:18Z","timestamp":1725681258924},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/iscas.2014.6865091","type":"proceedings-article","created":{"date-parts":[[2014,7,30]],"date-time":"2014-07-30T21:16:29Z","timestamp":1406754989000},"page":"165-168","source":"Crossref","is-referenced-by-count":18,"title":["A design approach to automatically synthesize ANSI-C assertions during High-Level Synthesis of hardware accelerators"],"prefix":"10.1109","author":[{"given":"Mohamed","family":"Ben Hammouda","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philippe","family":"Coussy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Loic","family":"Lagadec","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"13","first-page":"1","article-title":"PSL assertion checkers synthesis with ASM based HLS tool ABELITE","author":"maksim","year":"2012","journal-title":"Test Workshop (LATW)"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1007\/978-94-007-1125-9_8"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/HLDVT.2006.319966"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2010.5470747"},{"key":"2","first-page":"1318","article-title":"An introduction to assertion-based verification","author":"yunfeng","year":"2009","journal-title":"IEEE 8th International Conference on ASIC"},{"journal-title":"Scalable Hardware Verification with Symbolic Simulation","article-title":"Design and verification of digital systems","year":"2006","key":"1"},{"journal-title":"Open Verification Library Assertion Monitor Reference Manual","year":"2009","key":"10"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/92.894157"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2009.69"},{"key":"5","first-page":"1","article-title":"Assertion support in high-level synthesis design flow","author":"ribon","year":"2011","journal-title":"Proc FDL"},{"journal-title":"Codevelope's Users Guide","article-title":"Impulse accelerated technologies","year":"2008","key":"4"},{"journal-title":"SystemVerilog 3 la Language Reference Manuall","year":"2001","key":"9"},{"journal-title":"Property Specification Language Reference Manual Version 1 1","year":"2004","key":"8"}],"event":{"name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2014,6,1]]},"location":"Melbourne VIC, Australia","end":{"date-parts":[[2014,6,5]]}},"container-title":["2014 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6852006\/6865048\/06865091.pdf?arnumber=6865091","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T21:19:51Z","timestamp":1490303991000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6865091\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2014.6865091","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}