{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T14:54:51Z","timestamp":1761663291831},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/iscas.2014.6865338","type":"proceedings-article","created":{"date-parts":[[2014,7,30]],"date-time":"2014-07-30T17:16:29Z","timestamp":1406740589000},"page":"1126-1129","source":"Crossref","is-referenced-by-count":6,"title":["A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm CMOS process"],"prefix":"10.1109","author":[{"given":"Chua-Chin","family":"Wang","sequence":"first","affiliation":[]},{"given":"Chiang-Hsiang","family":"Liao","sequence":"additional","affiliation":[]},{"given":"Sih-Yu","family":"Chen","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2000459"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378632"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187538"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2004.1283650"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2010.2071690"},{"key":"6","first-page":"1","article-title":"Single-ended disturb-free 5t loadless sram cell using 90 nm cmos process","author":"chen","year":"2012","journal-title":"Proc IEEE Int Conf on IC Design & Technology (ICICDT)"},{"key":"5","first-page":"231","article-title":"An efficient methodology for generating optimal and uniform march tests","author":"al-harbi","year":"2011","journal-title":"Proc IEEE VLSI Test Symp (VTS)"},{"key":"4","first-page":"376","article-title":"A 153mb-sram design with dynamic stability enhancement and leakage reduction in 45 nm high-m metal-gate cmos technology","author":"hamzaoglu","year":"2008","journal-title":"Proc IEEE Int Solid-State Circuits Conf (ISSCC) Dig of Tech Papers"},{"key":"9","first-page":"72","article-title":"A 40-nm 0. 5-V 20. 1-gW\/MHz 8T SRAM with low-energy disturb mitigation scheme","author":"yoshimoto","year":"2011","journal-title":"Proc Symp on VLSI Circuits (VLSIC)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2159056"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2012.2198984"}],"event":{"name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2014,6,1]]},"location":"Melbourne VIC, Australia","end":{"date-parts":[[2014,6,5]]}},"container-title":["2014 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6852006\/6865048\/06865338.pdf?arnumber=6865338","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T17:00:55Z","timestamp":1490288455000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6865338\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2014.6865338","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}