{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,2]],"date-time":"2026-02-02T14:37:45Z","timestamp":1770043065497,"version":"3.49.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,6]]},"DOI":"10.1109\/iscas.2014.6865471","type":"proceedings-article","created":{"date-parts":[[2014,7,30]],"date-time":"2014-07-30T17:16:29Z","timestamp":1406740589000},"page":"1660-1663","source":"Crossref","is-referenced-by-count":18,"title":["TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs"],"prefix":"10.1109","author":[{"given":"Xifan","family":"Tang","sequence":"first","affiliation":[]},{"given":"Jian","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/4.293119"},{"key":"14","author":"golinescu","year":"1999","journal-title":"A 2 5 Gb\/s CMOS Add-Drop Multiplexer for ATM"},{"key":"11","year":"2009","journal-title":"Cadence Encounter Library Characterize User Guide"},{"key":"12","year":"0","journal-title":"Predictive Technology Model"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/4.553179"},{"key":"2","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746344"},{"key":"10","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1145\/2228360.2228369","article-title":"Physical synthesis onto sea-of-tiles with double-gate silicon nanowire transistors","author":"bobba","year":"2012","journal-title":"40th Design Automation Conference (DAC)"},{"key":"7","first-page":"841","article-title":"Polarity control in double-gate","author":"de marchi","year":"2012","journal-title":"Gate-All-Around Vertically Stacked Silicon Nanowire FETs International Electron Devices Meeting (IEDM)"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1063\/1.3280042"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2005.851427"},{"key":"4","first-page":"262","article-title":"A 9.7MW AAC-decoding","author":"nomura","year":"2008","journal-title":"620mW H 264 720p 60fps Decoding 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology ISSCC Dig Tech Papers"},{"key":"9","first-page":"2111","article-title":"Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETS","author":"zhang","year":"2013","journal-title":"IEEE International Symposium on Circuits and Systems (ISCAS)"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/EDST.2009.5166100"}],"event":{"name":"2014 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Melbourne VIC, Australia","start":{"date-parts":[[2014,6,1]]},"end":{"date-parts":[[2014,6,5]]}},"container-title":["2014 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6852006\/6865048\/06865471.pdf?arnumber=6865471","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T13:37:19Z","timestamp":1498138639000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6865471\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas.2014.6865471","relation":{},"subject":[],"published":{"date-parts":[[2014,6]]}}}