{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,12]],"date-time":"2025-04-12T20:40:47Z","timestamp":1744490447699},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168561","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T21:31:36Z","timestamp":1438291896000},"page":"25-28","source":"Crossref","is-referenced-by-count":4,"title":["Public key protocol for usage-based licensing of FPGA IP cores"],"prefix":"10.1109","author":[{"given":"Li","family":"Zhang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chip-Hong","family":"Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"article-title":"Protecting Multiple Cores in a Single FPGA Design","year":"2008","author":"drimer","key":"ref4"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1504\/IJES.2006.010166"},{"journal-title":"Helion Technology","article-title":"Overview datasheet - High performance AES (Rijndael) cores for Xilinx FPGA (Rev 2.4.0)","year":"2009","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2014.2355043"},{"journal-title":"Helion Technology","article-title":"Full datasheet - Fast hash core family for Xilinx FPGA (Rev 1.9)","year":"2011","key":"ref11"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2011.2169667"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2013.2282282"},{"key":"ref7","first-page":"63","article-title":"FPGA intrinsic PUFs and their use for IP protection","author":"guajardo","year":"2007","journal-title":"Proc CHES"},{"key":"ref2","first-page":"259","article-title":"Secure Configuration of a Field Programmable Gate Array","author":"kean","year":"2001","journal-title":"Proc FCCM"},{"year":"0","key":"ref9","article-title":"High-performance NIST P-256\/P-384 ECC Module"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/503062.503065"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168561.pdf?arnumber=7168561","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:15:24Z","timestamp":1490382924000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168561\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168561","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}