{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,29]],"date-time":"2026-09-29T16:04:03Z","timestamp":1790697843918,"version":"4.1.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168700","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T21:31:36Z","timestamp":1438291896000},"page":"581-584","source":"Crossref","is-referenced-by-count":15,"title":["Hyperbolic tangent passive resistive-type neuron"],"prefix":"10.1109","author":[{"given":"Jafar","family":"Shamsi","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amirali","family":"Amirsoleimani","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sattar","family":"Mirzakuchaki","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Arash","family":"Ahmade","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Shahpour","family":"Alirezaee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Majid","family":"Ahmadi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"67","article-title":"A reconfigurable VLSI neural network","volume":"27","author":"satyanarayana","year":"1989","journal-title":"Proc 1989 Intl Conf on Wafer Scale Integration"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1996.541638"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.1999.813409"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/82.964997"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126610006141"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008215706267"},{"key":"ref3","first-page":"712","article-title":"A programmable analog neural computer and simulator","author":"mueller","year":"1989"},{"key":"ref6","article-title":"Design of parallel hardware neural network systems from custom analog VLSI ‘building block’ chips. Neural Networks, 1989","author":"eberhardt","year":"1989","journal-title":"IJCNN International Joint Conference on"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2009.5118213"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2011.2109404"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1016\/j.neucom.2010.03.021"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"19","DOI":"10.1142\/S0129065700000041","article-title":"Neural networks in analog hardware-design and implementation issues","volume":"10","author":"draghici","year":"2000","journal-title":"Int J Neural Syst"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/2.485891"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1049\/el:19890211"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","location":"Lisbon, Portugal","start":{"date-parts":[[2015,5,24]]},"end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168700.pdf?arnumber=7168700","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,9,6]],"date-time":"2020-09-06T18:14:47Z","timestamp":1599416087000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168700\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168700","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}