{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,7]],"date-time":"2024-09-07T05:01:50Z","timestamp":1725685310670},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168704","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T17:31:36Z","timestamp":1438277496000},"page":"597-600","source":"Crossref","is-referenced-by-count":5,"title":["Ultra-low leakage sub-32nm TFET\/CMOS hybrid 32kb pseudo DualPort scratchpad with GHz speed for embedded applications"],"prefix":"10.1109","author":[{"given":"N.","family":"Gupta","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Makosiej","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"O.","family":"Thomas","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Amara","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Vladimirescu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"C.","family":"Anghel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"212","author":"nii","year":"2008","journal-title":"IEEE Symposium on VLSI Circuits"},{"key":"ref3","article-title":"A 90nm Dual-Port SRAM with 2.04&#x00B5;m2 8T-Thin Cell Using Dynamically-Controlled Column Bias Scheme","author":"nii","year":"2004","journal-title":"ISSCC"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.893580"},{"key":"ref6","first-page":"2517","author":"makosiej","year":"2012","journal-title":"ISCAS"},{"key":"ref5","first-page":"236","author":"fukuda","year":"2014","journal-title":"ISSCC"},{"key":"ref8","article-title":"FDSOI Process\/Design full solutions for Ultra Low Leakage, High Speed and Low Voltage SRAMs","author":"ranica","year":"2013","journal-title":"VLSI Symposium"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2011.2128320"},{"article-title":"A 45-nm Dual-Port SRAM Utilizing Write-Assist Cells Against Simultaneous Access Disturbances, TCAS 2012","year":"0","author":"jui-jen","key":"ref2"},{"key":"ref9","article-title":"Single-Ended Subthreshold SRAM With Asymmetrical Write\/Read-Assist","author":"ming-hsien","year":"2010","journal-title":"IEEE Transactions on Circuits and Systems"},{"first-page":"55","year":"2008","author":"noguchi","key":"ref1"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168704.pdf?arnumber=7168704","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T15:21:23Z","timestamp":1490368883000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168704\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168704","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}