{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,26]],"date-time":"2025-09-26T13:25:59Z","timestamp":1758893159838,"version":"3.28.0"},"reference-count":7,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168706","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T17:31:36Z","timestamp":1438277496000},"page":"605-608","source":"Crossref","is-referenced-by-count":6,"title":["A high-throughput HEVC deblocking filter VLSI architecture for 8k×4k application"],"prefix":"10.1109","author":[{"given":"Wei","family":"Cheng","sequence":"first","affiliation":[]},{"given":"Yibo","family":"Fan","sequence":"additional","affiliation":[]},{"given":"YanHeng","family":"Lu","sequence":"additional","affiliation":[]},{"given":"Yize","family":"Jin","sequence":"additional","affiliation":[]},{"given":"Xiaoyang","family":"Zeng","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","first-page":"2812","article-title":"A memory interleaving and interlacing architecture for Deblocking filter in H. 264\/AVC","volume":"56 4","author":"yeong-kang","year":"2010","journal-title":"Consumer Electronics IEEE Transactions on"},{"key":"ref3","first-page":"1967","article-title":"Acombincd SAO and Deblocking filter architecture for HEVC video decoder","author":"zhu","year":"2013","journal-title":"ICIP"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6571936"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645602"},{"key":"ref7","article-title":"High throughput VLSI architecture supporting HEVC loop filter for Ultra HDTV","author":"mihir","year":"2013","journal-title":"IEEE Third International Conference on Consumer Electronics-Berlin"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2223053"},{"key":"ref1","article-title":"High Efficiency Video Coding (HEVC) text specification draft 8","author":"bross","year":"2012","journal-title":"ITU - T SG16 WP3 and ISO\/IEC JTCl\/SC29\/WGII Document JCTVC-JI003"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168706.pdf?arnumber=7168706","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T15:24:30Z","timestamp":1490369070000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168706\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168706","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}