{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T16:08:56Z","timestamp":1761581336295,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168835","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T17:31:36Z","timestamp":1438277496000},"page":"1122-1125","source":"Crossref","is-referenced-by-count":9,"title":["Multiple layer parallel motion estimation on GPU for High Efficiency Video Coding (HEVC)"],"prefix":"10.1109","author":[{"given":"Falei","family":"Luo","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siwei","family":"Ma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Juncheng","family":"Ma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Honggang","family":"Qi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Li","family":"Su","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wen","family":"Gao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"NVIDIA Corporation","article-title":"NVIDIA CUDA C programming guide","year":"2014","key":"ref4"},{"key":"ref3","first-page":"73","article-title":"Low Complexity Rate Distortion Optimization for HEVC","volume":"73","author":"ma","year":"2013","journal-title":"Data Compression Conference"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2014.6775965"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2010.5418821"},{"key":"ref5","first-page":"697","article-title":"H.264\/AVC motion estimation implementation on compute unified device architecture (CUDA)","author":"chen","year":"2008","journal-title":"IEEE International Conference on Multimedia and Expo"},{"key":"ref8","first-page":"1","article-title":"Paralleling variable block size motion estimation of HEVC on CPU plus GPU platform","author":"wang","year":"2013","journal-title":"IEEE International Conference on Multimedia and Expo Workshops (ICMEW)"},{"key":"ref7","first-page":"633","article-title":"Variable block size motion estimation implementation on Compute Unified Device Architecture (CUDA)","author":"lee","year":"2013","journal-title":"IEEE International Conference on Consumer Electronics (ICCE)"},{"key":"ref2","first-page":"1","article-title":"Efficient SIMD optimization of HEVC encoder over x86 processors","author":"chen","year":"2012","journal-title":"Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA ASC)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2014.7025252"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168835.pdf?arnumber=7168835","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T15:36:23Z","timestamp":1490369783000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168835\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168835","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}