{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:04:50Z","timestamp":1730271890525,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168852","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T17:31:36Z","timestamp":1438277496000},"page":"1190-1193","source":"Crossref","is-referenced-by-count":1,"title":["Improving F&lt;inf&gt;max&lt;\/inf&gt; of FPGA circuits employing DPR to recover from configuration memory upsets"],"prefix":"10.1109","author":[{"given":"Ediz","family":"Cetin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Oliver","family":"Diessel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lingkan","family":"Gong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2004.834955"},{"key":"ref11","article-title":"Reduced Triple Modular Redundancy foc tolerating SEU s in SRAM-based FPGAs","author":"chandrasekhar","year":"2005","journal-title":"Military and Aerospace Programmable Logic Devices (MAPLD) Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2005.860674"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.229"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/36.29557"},{"key":"ref15","first-page":"43","article-title":"Synthetic aperture radar signal data compression using block adaptive quantization","author":"kuduvalli","year":"1994","journal-title":"Goddard Space Flight Center Science Information Management and Data Compression Workshop"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1960.1057548"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2007.25"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2011.6132703"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723154"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1404371.1404426"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2014.6865437"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2013.6645571"},{"key":"ref2","article-title":"Triple module redundancy design techniques for Virtex FPGAs","volume":"1","author":"carmichael","year":"2001","journal-title":"Xilinx App Note"},{"key":"ref1","first-page":"xapp216","volume":"0","author":"carmichael","year":"2000","journal-title":"Correcting Single-Event Upsets Through Virtex Partial Configuration"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2008.2000852"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168852.pdf?arnumber=7168852","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T15:29:38Z","timestamp":1490369378000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168852\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168852","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}