{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:13:57Z","timestamp":1729628037949,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7168912","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T21:31:36Z","timestamp":1438291896000},"page":"1430-1433","source":"Crossref","is-referenced-by-count":3,"title":["Efficient subquadratic parallel multiplier based on modified SPB of GF(2<sup>m<\/sup>)"],"prefix":"10.1109","author":[{"given":"Jeng-Shyang","family":"Pan","sequence":"first","affiliation":[]},{"given":"Pramod Kumar","family":"Meher","sequence":"additional","affiliation":[]},{"given":"Chiou-Yng","family":"Lee","sequence":"additional","affiliation":[]},{"given":"Hong-Hai","family":"Bai","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/TC.2007.19"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TC.2005.64"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"1169","DOI":"10.1109\/TC.2012.239","article-title":"Low-Latency Digit-Serial Systolic Double Basis Multiplier over GF(2m) Using Subquadratic Toeplitz Matrix-Vector Product Approach","volume":"63","author":"pan","year":"2014","journal-title":"IEEE Trans Computers"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/12.392853"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TC.2004.52"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TC.2012.95"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1007\/s11265-011-0654-2"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1016\/j.vlsi.2011.12.006","article-title":"Low complexity bit-parallel polynomial basis multipliers over binary fields for special irreducible pentanomials","volume":"46","author":"imana","year":"2013","journal-title":"Integration"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TC.2012.63"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/12.508323"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"297","DOI":"10.1007\/978-3-540-85538-5_20","article-title":"A Comparison Between Hardware Accelerators for the Modified Tate Pairing over F2m and F3m;","author":"beuchat","year":"2008","journal-title":"Second International Conference on Pairing-Based Cryptography - Pairing 2008"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07168912.pdf?arnumber=7168912","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,28]],"date-time":"2019-08-28T22:51:18Z","timestamp":1567032678000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7168912\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7168912","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}