{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,5]],"date-time":"2025-07-05T04:08:35Z","timestamp":1751688515514,"version":"3.28.0"},"reference-count":5,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,5]]},"DOI":"10.1109\/iscas.2015.7169321","type":"proceedings-article","created":{"date-parts":[[2015,7,30]],"date-time":"2015-07-30T21:31:36Z","timestamp":1438291896000},"page":"3012-3015","source":"Crossref","is-referenced-by-count":2,"title":["Subblock-level matching layout for analog block-pair and its manufacturability evaluation"],"prefix":"10.1109","author":[{"given":"Takuya","family":"Hirata","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryuta","family":"Nishino","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shigetoshi","family":"Nakatake","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masaya","family":"Shimoyama","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Masashi","family":"Miyagawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koichi","family":"Tanno","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Akihiro","family":"Yamada","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","first-page":"83","author":"kahng","year":"2007","journal-title":"Exploiting STI Stress for Performance Proc of International Conference on Computer-Aided Design (ICCAD)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2005.1568738"},{"key":"ref5","first-page":"696","volume":"95?c","author":"liu","year":"2012","journal-title":"Layout-Aware Variability Characterization of CMOS Current Sources IEICE Transactions"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1989.572629"},{"journal-title":"Design of Analog CMOS Integrated Circuits","year":"2003","author":"razavi","key":"ref1"}],"event":{"name":"2015 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2015,5,24]]},"location":"Lisbon, Portugal","end":{"date-parts":[[2015,5,27]]}},"container-title":["2015 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7152138\/7168553\/07169321.pdf?arnumber=7169321","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T19:27:08Z","timestamp":1490383628000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7169321\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,5]]},"references-count":5,"URL":"https:\/\/doi.org\/10.1109\/iscas.2015.7169321","relation":{},"subject":[],"published":{"date-parts":[[2015,5]]}}}