{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T23:02:40Z","timestamp":1725490960722},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,5]]},"DOI":"10.1109\/iscas.2017.8050235","type":"proceedings-article","created":{"date-parts":[[2017,9,28]],"date-time":"2017-09-28T16:33:32Z","timestamp":1506616412000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer vision"],"prefix":"10.1109","author":[{"given":"Prashant","family":"Dubey","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kritika","family":"Aditya","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ankur","family":"Srivastava","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amit","family":"Khanuja","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jamil","family":"Kawa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Thu","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2001872"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2013766"},{"key":"ref10","first-page":"1","article-title":"Ieee standard for memory modeling in core test language","year":"2014","journal-title":"IEEE Std 1450 6 2&#x2013;2014"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2282614"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2015.10"},{"key":"ref8","first-page":"313","article-title":"A low-power cell-based-design multi-port register file in 65nm cmos technology","year":"2010","journal-title":"Proceedings of 2010 IEEE International Symposium on Circuits and Systems"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MWSCAS.2010.5548579"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.604091"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2012.6243818"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2016.7418008"}],"event":{"name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2017,5,28]]},"location":"Baltimore, MD, USA","end":{"date-parts":[[2017,5,31]]}},"container-title":["2017 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8014728\/8049747\/08050235.pdf?arnumber=8050235","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,27]],"date-time":"2017-10-27T17:27:10Z","timestamp":1509125230000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8050235\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iscas.2017.8050235","relation":{},"subject":[],"published":{"date-parts":[[2017,5]]}}}