{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T21:30:47Z","timestamp":1725399047620},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,5]]},"DOI":"10.1109\/iscas.2017.8050702","type":"proceedings-article","created":{"date-parts":[[2017,9,28]],"date-time":"2017-09-28T16:33:32Z","timestamp":1506616412000},"page":"1-4","source":"Crossref","is-referenced-by-count":10,"title":["High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos"],"prefix":"10.1109","author":[{"given":"Marcel","family":"Correa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruno","family":"Zatt","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcelo","family":"Porto","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luciano","family":"Agostini","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2015.2428571"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7538911"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-06895-4_4"},{"journal-title":"JCT-VC 7thh Meeting","article-title":"JCTVC-C207 Encoder improvement of unified intra prediction","year":"2010","key":"ref13"},{"journal-title":"JCT-VC 7thh Meeting","article-title":"JCTVC-L1100 Common test conditions and software configurations","year":"2013","key":"ref14"},{"journal-title":"ITU-R BT 2020","article-title":"Parameter values for ultra-high definition television systems for production and international programme exchange","year":"2012","key":"ref15"},{"year":"2003","key":"ref4"},{"year":"2013","key":"ref3"},{"key":"ref6","article-title":"A highly pipelined VLSI architecture for all modes and block size intra prediction in HEVC encoder","author":"liu","year":"2013","journal-title":"IEEE 10th International Conference on ASIC (ASICON)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICIP.2012.6466830"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742917"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/PCS.2013.6737693"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSVT.2012.2221191"},{"key":"ref1","doi-asserted-by":"crossref","DOI":"10.1002\/0470869615","author":"richardson","year":"2003","journal-title":"H 264 and MPEG-4 Video Compression Video Coding for Next-Generation Multimedia"},{"key":"ref9","article-title":"A 1062Mpixels\/s 8192&#x00D7;4320p high efficiency video coding (H.265) encoder chip","author":"tsai","year":"2013","journal-title":"Symposium on VLSI Circuits (VLSIC)"}],"event":{"name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2017,5,28]]},"location":"Baltimore, MD, USA","end":{"date-parts":[[2017,5,31]]}},"container-title":["2017 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8014728\/8049747\/08050702.pdf?arnumber=8050702","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,3]],"date-time":"2019-10-03T22:12:39Z","timestamp":1570140759000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8050702\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iscas.2017.8050702","relation":{},"subject":[],"published":{"date-parts":[[2017,5]]}}}