{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T16:42:50Z","timestamp":1765039370532},"reference-count":6,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,5]]},"DOI":"10.1109\/iscas.2017.8050918","type":"proceedings-article","created":{"date-parts":[[2017,9,28]],"date-time":"2017-09-28T20:33:32Z","timestamp":1506630812000},"page":"1-4","source":"Crossref","is-referenced-by-count":10,"title":["28-nm 1T-1MTJ 8Mb 64 I\/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier"],"prefix":"10.1109","author":[{"given":"Artur","family":"Antonyan","sequence":"first","affiliation":[]},{"given":"Suksoo","family":"Pyo","sequence":"additional","affiliation":[]},{"given":"Hyuntaek","family":"Jung","sequence":"additional","affiliation":[]},{"given":"Gwan-Hyeob","family":"Koh","sequence":"additional","affiliation":[]},{"given":"Taejoong","family":"Song","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2010.5433948"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2088143"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2468971"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7062962"},{"key":"ref2","first-page":"143","article-title":"Technology comparison for large last-level caches (L3Cs)","author":"chang","year":"2013","journal-title":"HPCA2013 IEEE 19th International Symposium on"},{"key":"ref1","first-page":"247","article-title":"Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM","author":"lee","year":"2012","journal-title":"SoC Design ISOCC"}],"event":{"name":"2017 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2017,5,28]]},"location":"Baltimore, MD, USA","end":{"date-parts":[[2017,5,31]]}},"container-title":["2017 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8014728\/8049747\/08050918.pdf?arnumber=8050918","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,10,27]],"date-time":"2017-10-27T21:49:21Z","timestamp":1509140961000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8050918\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,5]]},"references-count":6,"URL":"https:\/\/doi.org\/10.1109\/iscas.2017.8050918","relation":{},"subject":[],"published":{"date-parts":[[2017,5]]}}}