{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T01:32:42Z","timestamp":1725759162531},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,5]]},"DOI":"10.1109\/iscas.2018.8350917","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-4","source":"Crossref","is-referenced-by-count":1,"title":["Fast Timing Analysis of Transistor-Level Full Custom Digital Circuits"],"prefix":"10.1109","author":[{"given":"Jingon","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jinwook","family":"Jung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngsoo","family":"Shin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1142\/S0218126606003143"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/43.45867"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1987.1270271"},{"journal-title":"Circuits Interconnections and Packaging for VLSI","year":"1990","author":"bakoglu","key":"ref13"},{"journal-title":"Timing","year":"2004","author":"sapatnekar","key":"ref14"},{"journal-title":"ISCAS'85 Benchmarks Circuits","year":"0","key":"ref15"},{"journal-title":"HSPICE Users Guide","year":"2015","key":"ref16"},{"journal-title":"CustomSim User Guide","year":"2015","key":"ref17"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/378239.378486"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.859510"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545648"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2015.7372653"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1016\/0165-6074(92)90387-M"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907068"},{"journal-title":"CMOS VLSI Design","year":"2010","author":"weste","key":"ref2"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337602"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1998.705281"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08350917.pdf?arnumber=8350917","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:54:03Z","timestamp":1571691243000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8350917\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8350917","relation":{},"subject":[],"published":{"date-parts":[[2018,5]]}}}