{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:10:39Z","timestamp":1730272239458,"version":"3.28.0"},"reference-count":28,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8350936","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-5","source":"Crossref","is-referenced-by-count":9,"title":["Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation"],"prefix":"10.1109","author":[{"given":"Adeboye Stephen","family":"Oyeniran","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Siavoosh Payandeh","family":"Azad","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Raimund","family":"Ubar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"411","article-title":"A BIST Methodology for Iterative Logic Arrays","volume":"1","author":"su","year":"1992","journal-title":"IEEE Int Symp Circuits and Systems"},{"key":"ref11","first-page":"680","article-title":"Computer-Aided Design of Pseudo-exhaustive BIST for Semiregular Circuits","author":"su","year":"1990","journal-title":"Proc Int Test Conf"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1981.1675715"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/SECON.2010.5453929"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676480"},{"key":"ref15","first-page":"284","article-title":"Test Generation for Arithmetic Units by Graph Labeling","author":"chatterjee","year":"1987","journal-title":"Proc IEEE Int Symp FTC"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1988.5322"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/43.87603"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/ETC.1989.36255"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1995.529914"},{"year":"0","key":"ref28"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1984.1676477"},{"key":"ref27","article-title":"Instruction level test for parallel multipliers","author":"lin","year":"2008","journal-title":"15th IEEE International Conference on Electronics Circuits and Systems ICECS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.795222"},{"key":"ref6","first-page":"522","article-title":"Reconfigurable Hardware for Pseudo-Exhaustive Test","author":"udell","year":"1988","journal-title":"International Test Conference"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1989.105582"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.108616"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FTCS.1988.5294"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.913755"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICASIC.2001.982669"},{"key":"ref1","article-title":"BIST of Digital Signal Processors in Virtex-4 FPGAs","author":"pulukuri","year":"2009","journal-title":"Proc IEEE Southeastern Symp Syst Theory"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/12.795222"},{"key":"ref22","article-title":"Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays","volume":"49","author":"psarakis","year":"2000","journal-title":"IEEE Trans on Comp"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1093\/qjmam\/4.2.236"},{"key":"ref24","first-page":"342","article-title":"Model for Delay faults Based upon Paths","author":"smith","year":"1985","journal-title":"IEEE Int Test Conference"},{"key":"ref23","article-title":"Paschalis. Built-In Sequential Fault Self-Testing of Array Multipliers","volume":"24","author":"psarakis","year":"2005","journal-title":"IEEE Trans CAD IC Syst"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2008.63"},{"key":"ref25","article-title":"Testing TDF in Modified Booth Multipliers by Using C-Testable and SIC patterns","author":"liang","year":"2007","journal-title":"TENCON IEEE Region 10 Conf"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08350936.pdf?arnumber=8350936","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:52:20Z","timestamp":1571691140000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8350936\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":28,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8350936","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}