{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T16:50:43Z","timestamp":1725468643057},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8351162","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["IbIS: Interface-based Interconnection Structure for Dynamically Reconfigurable FPGAs"],"prefix":"10.1109","author":[{"given":"Ludovica","family":"Bozzoli","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luca","family":"Sterpone","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ReConFig.2012.6416740"},{"key":"ref11","first-page":"236","article-title":"Placement of Intermodule Connections on Partially Reconfigurable Devices","author":"dittmann","year":"2005","journal-title":"IEEE Symposium on Integrated Circuits and Systems Design"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2008.0097"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-73625-7_29"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927025"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/12.773796"},{"journal-title":"AMBA® AXI Protocol v1 0 Specification ARM IHI 0022B","year":"2003","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CSIE.2009.233"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2013.80"},{"journal-title":"Revision B 3","article-title":"WISHBONE SoC Architecture Specification","year":"0","key":"ref7"},{"key":"ref2","article-title":"Design-space exploration of the configurable 32 bit VLIW processor Core V A for signal processing applications","author":"sievers","year":"2013","journal-title":"IEEE Norchip"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2044902"},{"key":"ref9","first-page":"1","article-title":"Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs","author":"hagemeyer","year":"2007","journal-title":"IEEE International Conference on Engineering of Reconfigurable Systems and Algorithms"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351162.pdf?arnumber=8351162","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:54:05Z","timestamp":1571691245000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351162\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351162","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}