{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T07:12:58Z","timestamp":1730272378088,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018]]},"DOI":"10.1109\/iscas.2018.8351291","type":"proceedings-article","created":{"date-parts":[[2018,5,4]],"date-time":"2018-05-04T18:00:05Z","timestamp":1525456805000},"page":"1-5","source":"Crossref","is-referenced-by-count":2,"title":["Video Service Function Chaining with a Real-time Packet Reordering Circuit"],"prefix":"10.1109","author":[{"given":"Yuta","family":"Ukon","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koji","family":"Yamazaki","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Koyo","family":"Nitta","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"A flexible and high-performance communication between FPGA and CPU for NFV Applications utilizing DPDK RingQueue","author":"shibata","year":"2016","journal-title":"ACM\/EDAC\/IEEE 53rd Design Automation Conference (DAC)"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2015.7477471"},{"journal-title":"Intel Intel DPDK Reorder Library","year":"0","key":"ref12"},{"key":"ref13","first-page":"886","article-title":"Histograms of oriented gradients for human detection","volume":"1","author":"navneet","year":"2005","journal-title":"Computer Vision and Pattern Recognition (CVPR)"},{"journal-title":"Intel Intel FPGA SDK for OpenCL Overview","year":"0","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.17487\/RFC7665"},{"key":"ref3","article-title":"Xeon+ FPGA platform for the data center","volume":"119","author":"gupta","year":"2015","journal-title":"Workshop on the Intersections of Computer Architecture and Reconfigurable Logic"},{"journal-title":"A Linux Foundation Collaborative Project Production Quality Multilayer Open Virtual Switch","year":"0","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2015.2477041"},{"journal-title":"Ryu SDN Framework Community COMPONENT-BASED SOFT-WARE DEFINED NETWORKING FRAMEWORK-Build SDN Agilely","year":"0","key":"ref8"},{"journal-title":"NTT Lagopus switch-a high performance software OpenFlow 1 3 switch","year":"0","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref1","article-title":"FPGA Accelerated Computing Using AWS F1 Instances","author":"pellerin","year":"2017","journal-title":"AWS Public Sector Summit 2017"},{"key":"ref9","first-page":"1","article-title":"A PCIe DMA engine to support the virtualization of 40 Gbps FPGA-accelerated network appliances","author":"fernando","year":"2015","journal-title":"Re-ConFigurable Computing and FPGAs (ReConFig)"}],"event":{"name":"2018 IEEE International Symposium on Circuits and Systems (ISCAS)","start":{"date-parts":[[2018,5,27]]},"location":"Florence","end":{"date-parts":[[2018,5,30]]}},"container-title":["2018 IEEE International Symposium on Circuits and Systems (ISCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8334884\/8350884\/08351291.pdf?arnumber=8351291","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,10,21]],"date-time":"2019-10-21T20:53:40Z","timestamp":1571691220000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8351291\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iscas.2018.8351291","relation":{},"subject":[],"published":{"date-parts":[[2018]]}}}